hanbit hm d4m32m8gl url: www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0. (august. 2002) 1 general description the HMD4M32M8GL is a 4m x 32bit dynamic ram high - density memory module. the module consists of eight cmos 4m x 4bit drams in 24 - pin soj packages mounted on a 72 - pin, double - sided, fr - 4 - printed circuit board. a 0.1 or 0.22uf d ecoupling capacitor is mounted on the printed circuit board for each dram components. the module is a single in - line memory module with edge connections and is intended for mounting in to 72 - pin edge connector sockets. all module components may be powered from a single 5v dc power supply and all inputs and outputs are ttl - compatible. features w part identification HMD4M32M8GL - 4,096 cycles/64ms ref . gold w access times : 50, 60ns w high - density 16mbyte design w single + 5v 0.5v power supply w jedec standard pinout w fp(fast page) mode operation w ttl compatible inputs and outputs w fr4 - pcb design option s marking w timing 50 n s access - 5 60 n s access - 6 w packages 72 - pin simm m pin configuration de scription pin name function a0 C a11 address input(4k ref.) a0 C a10 address input(2k ref.) dq0 - 31 data in/out /we0 - /we3 read/write input /oe data output enable /cas colu mn address strobe /ras row address strobe bd in board insertion signal size size indentification vcc / vss power and ground nc no connection pin symbol pin symbol pin symbol 1 vss 25 dq2 2 49 dq 8 2 dq0 26 dq7 50 dq2 4 3 dq1 6 27 dq2 3 51 dq 9 4 dq1 28 a8 52 dq2 5 5 dq1 7 29 a1 0 53 dq1 0 6 dq2 30 vcc 54 dq2 6 7 dq 18 31 / we2 55 dq1 1 8 dq3 32 nc 56 dq 27 9 dq 19 33 vss 57 dq1 2 10 vcc 34 /ras 58 dq 28 11 /we0 35 vcc 59 /we3 12 a0 36 nc 60 dq 29 13 a1 37 nc 61 dq1 3 14 a2 38 /oe0 62 dq 30 15 a3 39 vss 63 dq1 4 16 a4 4 0 /cas 64 dq3 1 17 a5 41 vcc 65 dq1 5 18 a6 42 nc 66 vss 19 a7 43 nc 67 nc 20 dq4 44 nc 68 nc 21 dq2 0 45 a9 69 bd in 22 dq5 46 a11 70 nc 23 dq2 1 47 /w e1 71 size 24 dq6 48 vcc 72 vss 16mbyte(4mx32) fast page mode, 4k refresh 72pin simm part no. hm d4m32m8gl pin assignment
hanbit hm d4m32m8gl url: www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0. (august. 2002) 2 functional block dia gram /cas /ras /we0 /we1 /we2 /we3 / oe a0 - a10(a11) dq0 cas dq1 ras dq2 w oe a0 - a10(a11) dq3 u 1 dq0 cas dq1 ras dq2 w oe a0 - a10(a11) dq3 u2 dq0 cas dq1 ras dq2 w oe a0 - a10(a11) dq3 u 3 dq0 cas dq1 ras dq2 w oe a0 - a10(a11) dq3 u 4 dq0 cas dq1 ras dq2 w oe a0 - a10(a11) dq3 u 5 dq0 cas dq1 ras dq2 oe w a0 - a10(a11) dq3 u 6 dq0 cas dq1 ras dq2 w oe a0 - a10(a11) dq3 u 7 dq0 cas dq1 ras dq2 w oe a0 - a10(a11) dq3 u 8 dq0 - dq3 dq4 - dq7 dq8 - dq11 dq12 - dq15 dq16 - dq 19 dq20 - dq23 dq24 - dq27 dq28 - dq31 vcc vss 0.1uf or 0.22uf capacitor for each dram to all drams
hanbit hm d4m32m8gl url: www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0. (august. 2002) 3 absolute maximum rat ings parameter symbol rating voltage on any pin relativ e to vss v in ,out - 1v to 7.0v voltage on vcc supply relative to vss vcc - 1v to 7.0v power dissipation p d 8w storage temperature t stg - 55 o c to 150 o c short circuit output current i os 50ma w permanent device damage may occur if " absolute maximum ratings " are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditi ons ( voltage reference to v ss , t a =0 to 70 o c ) parameter symbol min typ max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.4 - vcc+1 v input low voltage v il - 1.0 - 0.8 v dc and operating cha r acteristics symbol speed min max units i cc1 - 5 - 6 - - 72 0 64 0 ma ma i cc2 - 16 ma i cc3 - 5 - 6 - - 720 640 ma ma i cc4 - 5 - 6 - - 640 560 ma ma i cc5 - 8 ma i cc6 - 5 - 6 - - 720 640 ma ma i l(l) i o(l) - 40 - 40 40 40 m a m a v oh v ol 2.4 - - 0.4 v v i cc 1 : operating current * (/ras , /cas , address cycling @t rc =min.) i cc2 : standby current ( /ras=/cas=v ih ) i cc3 : /ras only refresh current * ( /cas=v ih , /ras, address cycling @t rc =min ) i cc4 : fast page mode current * (/ras=v il , /cas, address cycling @t p c =min )
hanbit hm d4m32m8gl url: www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0. (august. 2002) 4 i cc5 : standby current (/ras=/cas=vcc - 0.2v ) i cc6 : /cas - before - /ras refresh current * (/ras and /cas cycling @t rc =min ) i il : input leakage current (any input 0v v in 6.5v, all other pins not under test = 0v) i ol : output leakage current (data out is disabled, 0v v out 5.5v v oh : output high voltage level (i oh = - 5ma ) v ol : output low voltage level (i ol = 4.2ma ) * note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address cad be changed maximum once while /ras=v il . in i cc4 , address can be changed maximum once within one page mode cycle. capacitance ( t a =25 o c, vcc = 5v, f = 1mz ) descri ption symbol min max units input capacitance (a0 - a1 1 ) c in1 - 40 pf input capacitance (/w e0 - /we3 ) c in2 - 49 pf input capacitance (/ras) c in3 - 49 pf input capacitance (/cas) c in4 - 49 pf input/output capacitance (dq0 - 31) c dq1 - 49 pf ac characterist ics ( 0 o c t a 70 o c , vcc = 5v 10%, see notes 1,2.) - 5 - 6 standard operation symbol min max min max unit random read or write cycle time t rc 90 110 ns access time from /ras t rac 50 60 ns access time from /cas t cac 13 15 ns access time from column address t aa 25 30 ns /cas to output in low - z t clz 0 0 ns output buffer turn - off delay t off 0 13 0 15 ns transition time (rise and fall) t t 3 50 3 50 ns /ras precharge time t rp 30 40 ns /ras pulse width t ras 50 10k 60 10k ns /ras hold time t rsh 13 15 ns /cas hold time t csh 50 60 ns /cas pulse width t cas 13 10k 15 10k ns /ras to /cas delay time t rcd 20 3 7 20 45 ns /ras to column address delay time t rad 15 25 15 30 ns /cas to /ras precharge time t crp 5 5 ns row address set - up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set - up time t asc 0 0 ns
hanbit hm d4m32m8gl url: www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0. (august. 2002) 5 column add ress hold time t cah 10 10 ns column address hold referenced to /ras t ar 40 45 ns column address to /ras lead time t ral 25 30 ns read command set - up time t rcs 0 0 ns read command hold referenced to /cas t rch 0 0 ns read command hold referenced to /ras t rrh 0 0 ns write command hold time t wch 10 10 ns write command hold referenced to /ras t wcr 40 45 ns write command pulse width t wp 10 10 ns write command to /ras lead time t rwl 15 15 ns write command to /cas lead time t cwl 13 15 ns data - in set - up time t ds 0 0 ns data - in hold time t dh 10 15 ns data - in hold referenced to /ras t dhr 40 45 ns refresh period 2k ref. t ref 32 32 ns write command set - up time t wcs 0 0 ns /cas setup time (c - b - r refresh) t csr 5 5 ns /cas hold time ( c - b - r refresh) t chr 10 10 ns /ras precharge to /cas hold time t rpc 5 5 ns access time from /cas precharge t cpa 30 35 ns fast page mode cycle time t pc 35 40 ns /cas precharge time (fast page) t cp 10 10 ns /ras pulse width (fast pa ge ) t rasp 50 200k 60 200k ns /w to /ras precharge time (c - b - r refresh) t wrp 10 10 ns /w to /ras hold time (c - b - r refresh) t wrh 10 10 ns /cas precharge(c - b - r counter test) t cpt 20 20 ns notes 1. an initial pause of 200 m s is required after power - up followed by any 8 /ras - only or /cas - before - /ras refresh cycles before proper device operation is achieved. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih(min) and v il(max) an d are assumed to be 5ns for all inputs. 3. measured with a load equivalent to 2ttl loads and 100pf 4. operation within the t rcd(max) limit insures that t rac(max) can be met. t rcd(max) is specified as a reference point only. if t rcd is greater than the specified t rcd(max) limit, then access time is controlled exclusively by t cac . 5. assumes that t rcd 3 t rcd(max) 6. t ar , t wcr , t dhr are referenced to t rad(max) 7.this parameter defines the time at which the output achieves the open circuit condition and is not reference d to v oh or v ol . 8. t wcs , t rwd , t cwd and t awd are non restrictive operating parameter. they are included in the data sheet as electrical characteristic only. if t wcs 3 twcs(min) the cycle is an early write
hanbit hm d4m32m8gl url: www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0. (august. 2002) 6 cycle and the data out pin will remain high impedance for the duration of the cycle. 9. either t rch or t rrh must be satisfied for a read cycle. 10. these parameters are referenced to the /cas leading edge in early write cycles and to the /w leading edge in read - write cycles. 11. operation withi n the t rad(max) limit insures that t rac(max) can be met. t rad(max) is specified as a reference point only. if t rad is greater than the specified t rad(max) limit. then access time is controlled by t aa . timing diagram please refer to attached timing d iagram chart (i)
hanbit hm d4m32m8gl url: www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0. (august. 2002) 7
hanbit hm d4m32m8gl url: www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0. (august. 2002) 8
hanbit hm d4m32m8gl url: www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0. (august. 2002) 9 pa ckaging information simm design o r dering information part number density org. package refresh cycle vcc speed HMD4M32M8GL - 5 16mbyte 4mx 32bit 72 pin - simm 4k cycles 64ms ref. 5.0v 50ns hmd4m 32m8gl - 6 16mbyte 4mx 32bit 72 pin - simm 4k cycles 64ms ref. 5.0v 60ns 1.2 7 0.08 m 0.25 mm max 2.54 mm min 1.27 gold : 1.04 0. 10 mm solder:0.914 0.10mm 25.4 0.2mm 6.35 0.2mm 95.25 0.2mm 6.35 0. 2mm 6.35 0.2mm 3.38 0.2mm
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